The fabrication of semiconductor devices requires the interconnection of different metal layers on the semiconductor device. The metal layers are typically separated by an isolation material generally referred to as intermediate dielectric.
Standard techniques for interconnecting the metal layers through the intermediate dielectric are termed the "via process" wherein a hole is etched through the intermediate dielectric to form a via or access to the lower level metallization, and the hole is filled with a conductive material which serves to interconnect the lower metallization layer with an upper metallization layer.
Various problems arise in the formation of the vias and the conductive materials in the vias which connect the upper and lower metallization layers. Significant problems arise when the sidewalls of the via are not sloped at the optimum angle for forming the metal material which connects the upper and lower metallization layers. Additional problems arise from misalignment of the via over the appropriate structures on the upper and lower metallization layers. The misalignment and misalignment tolerances required for the via process dictate either reduced packing densities for structures on the device, or down sized vias which lead to increased current density and resistance in the conductive material which fills the via.
Accordingly, it has been found desirable to provide a method for forming conductive pillars from lower level metallization interconnects to upper level metallization layers by processes which facilitate an increased packing density of structures on the device and a decreased current density in the conductive pillars between metallization layers.